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PE4251
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4250 SPDT switch. The RF common port is
connected through a 50 ? transmission line to the
bottom SMA connector, J3. Port 1 and Port 2 are
connected through 50 ? transmission lines to two
SMA connectors on either side of the board, J4 and
J2. A through transmission line connects SMA
connectors J5 and J6. This transmission line can be
used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.0322”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.033”, trace
gaps of 0.010”, dielectric thickness of 0.028”, copper
thickness of 0.0021” and ε r of 4.3.
J1 provides a means for controlling the DC inputs to
the device. The second-to-bottom lower right pin
(J1-3) is connected to the device V1 input. The
second-to-top upper right pin (J1-7) is connected to
the device V2 input. Footprints for decoupling
capacitors are provided on both V1 and V2 traces. It
is the responsibility of the customer to determine
proper supply decoupling for their design application.
Removing these components from the evaluation
board has not been shown to degrade RF
performance.
J1
HEADER 2 X 5 PIN
Figure 4. Evaluation Board Layouts
Peregrine specification 101/0337
Figure 5. Evaluation Board Schematic
Peregrine specification 102/0408
NOTES:
1. USE 101-0337-02 PCB.
2
4
6
8
10
2
4
6
8
10
1
3
5
7
9
1
3
5
7
9
2. CAUTION:
CONTAINS PARTS AND ASSEMBLIES SUSCEPTIBLE
TO DAMAGE BY ELECTROSTATIC DISCHARGE (ESD)
3. ALL TRANSMISION LINES ARE:
33MIL WIDTH, 10MIL GAPS, 28MIL CORE DIELECTRIC
4.3 Er AND 2.1MIL Cu
C1
100pF
R1
DNI
C2
100pF
R2
0 OHM
R3
0 OHM
THICKNESS.
J2
SMASM
U1
MSOP
1
J3
SMASM
1
1
2
3
4
V2
V1
RFC
N/C
RF2
GNDS2
GNDS1
RF1
8
7
6
5
J4
SMASM
or GND
1
J5
SMASM
1
1
J6
SMASM
?2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0255-02 │ UltraCMOS? RFIC Solutions
Page 4 of 9
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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